Fabrication of trenches--i.e., grooves etched in the substrate of an integrated circuit which (regardless of their length) have an aspect ratio (depth to width ratio) greater than approximately 1:1--is desirable in several areas of ULSI (ultra large scale integration) processing. Trench etch processing has become critical to the fabrication of state-of-the-art electronic devices exploiting three dimensional structural concepts such as trench capacitors, trench isolation, and trench transistors. However, fabrication of such trench strucures presents several distinctive difficulties at which the present invention is aimed.
There are many problems associated with trench etch processing. Some of these include achieving an acceptable etch rate, etch rate uniformity, etch selectivity, mask selectivity, mask type, critical dimension control, silicon surface defects, reactant loading and reactor residue buildup.
However, another set of problems concern the characteristics of the silicon trench itself, which characteristics must be carefully controlled to achieve satisfactory results in the applications proposed for trench structures. The trench cross-sectional profile is of particular concern: for instance, trench profiles where the silicon is undercut with respect to the patterning mask or where "grooving" (also termed "cusping") is exhibited near the bottom of the trench are commonly observed with conventional trench etch processing. Such undercutting and grooving are extremely undesirable in ULSI applications. Even minutely undercut sidewall profiles will readily promote void formation during the subsequent CVD refill operations commonly used in typical device processing. These voids are a problem because they can act as a contaminant depository. Moreover, a later etchback step may reopen the void, producing filament problems if a conductor is sought to be patterned thereafter. Moreover, etchback to achieve a truly planar surface within the trench, as is desirable for some advanced processes, becomes impossible. The trench bottom "grooving" can also be exceedingly deleterious: it can degrade the dielectric integrity of a trench capacitor and can promote high, stress-related Si defect densities during thick thermal oxidation.
Additional structural features in trench profiles commonly considered damaging for device applications include trench sidewall "ledges", rough silicon sidewall surfaces, a negative slope on the trench sidewall profile and trench sidewall nonlinearity.
Another problem of the prior art is a peculiar form of undercut which may be referred to as retrograde undercut, or bowing. This is different from the ordinary forms of undercut in that the amount of undercut will be almost zero next to the mask, and will typically increase with depth for a distance of a micron or more.
In applicant's co-pending parent applications, Ser. Nos. 026,491; 841,391; 841,502; and 730,701, applicant disclosed methods for trench fabrication in a relatively low pressure batch etcher environment. In these applications a batch reactive ion etching ("RIE") reactor process is disclosed having trench etch capability. The disclosed processes operate at low process pressures (less than 20 millitorr) emphasizing electron-impact ionization processes, so surface ion-impact processes dominate over neutral radical processes. The ion directionality and low pressure conditions contribute to the trench profile control which is critical to subsequent successful trench processing and good device performance. Batch systems overcome the wafer throughput limitations associated with deep silicon etching by processing a large number of wafers at a moderate etch rate, effecting a large equivalent single-wafer etch rate exceeding one micron per minute. Finally, batch processing permits multiple steps without significantly degrading wafer throughput. By manipulation of the process chemistry the trench structure can be tailored as a function of depth to eliminate or avoid trench structural defects that occur at several levels.
It has been proposed, however, that conventional batch reactors and, consequently, batch reactor processes are less than optimally suited for production environments. The present invention, alternatively, proposes a single wafer trench etching process which avoids limitations arising from the batch processing environment. Among the limitations of batch reactor capabilities for trench etch processes are the following:
(a) they are very expensive compared to competitive single-wafer dry etchers, particularly when retrofitted with a load lock assembly critical to operator safety and process capability and reproducibility; PA0 (b) they exhibit very poor Si: Photoresist etch rate ratios; PA0 (c) they exhibit relatively high etch rate and trench profile nonuniformities from position-to-position within the reactor (critical considerations when etching silicon trenches where an etch stop substrate often does not exist); PA0 (d) they exhibit strong loading effects since low flows are used relative to both the number of wafers and degree of ion bombardment which significantly lowers the silicon etch rate when the exposed silicon area is enlarged beyond a small percentage; PA0 (e) they are very difficult to clean up and for processes that have a tendency to deposit material on the chamber walls (as is characteristic of the trench etch), the forced down time is almost intolerable; PA0 (f) they are very difficult to qualify due to the large number of positions in the reactor (for trench etch, each position requires SEM analysis of the trench profile). Furthermore, frequent qualification of the reactor is required for trench processing since wafer-substrate contact can readily degrade, driving poor profiles, and the frequent difficult clean ups involve mechanical hardware adjustment which merits subsequent requalification; PA0 (g) endemic to batch processing is the inability to perform customized end point assessment for each wafer; PA0 (h) due to the expense of each wafer, which is increasing as wafer sizing increases, it is imprudent to commit a large number of wafers to a single run due to the extreme financial liability associated with the processing; PA0 (i) it is very difficult to develop processes in batch systems due to the time involved in conducting each experiment (which may be as long as 3-4 hours for a trench etch experiment) and the difficulty in establishing a "batch" process once successful results are achieved on a single wafer/position. PA0 (a) Improved etch rates; PA0 (b) Improved etch ratios; PA0 (c) Improved trench profile control; PA0 (d) Positive slope trench sidewall for facile refill processing; PA0 (e) Eliminates trench bottom "cusping" if there is a tendency; PA0 (f) Eliminates sidewall ledges; PA0 (g) Protects directly, or by shadowing, the sidewall from ion bombardment, reducing radiation damage; PA0 (h) Provides linear sidewalls; PA0 (i) Provides smooth, clean sidewalls; PA0 (j) Eliminates retrograde bowing; PA0 (k) Eliminates any tendency to etch laterally or undercut, especially buried n+ layers; PA0 (l) No loss of critical dimension defined lithographically, that is, line width loss is non-existent; PA0 (m) High etch rate uniformity across the slice; PA0 (n) Allows for customized end point assessment for each wafer; PA0 (o) Provides a process which is relatively clean--not resulting in formation of deposits or precipitates on the walls of the reactor vessel; PA0 (p) Provides a process which can be carried out in a single slice reactor which is relatively inexpensive, easy to clean, and for which it is relatively easy to optimize processes in comparison with batch reactors.
Accordingly, it is considered desirable to conduct trench etch processes on a slice by slice basis in a single slice reactor. However, prior art attempts at single wafer trench etching have failed or been unacceptable for a variety of reasons including poor trench profile control and/or low etch rates for silicon.